As representative electronic components, there are known semiconductor elements such as a bare chip, a CSP (Chip-sized Package) and a BGA (Ball Grid Array) that are widely used in various kinds of electronic equipments. As electronic equipments rapidly develop, such semiconductor elements are required to have higher function than before. As a semiconductor element has higher function, a multi-pin configuration is required in accordance with increase in the number of input and output terminals of the semiconductor element, and a reduction in length of a signal transmission wiring is required in order to achieve a high-speed operation of the semiconductor element. A flip-chip connection is known as a mounting technique developed for accomplishing these requirements.
The flip-chip connection is suitable for the multi-pin configuration because many electrode pads can be provided on an area of a wiring plane of a semiconductor element. Moreover, as compared with other connection methods such as wire bonding and tape automated bonding, according to the flip-chip connection, the electrode pad of the semiconductor element is directly connected to a pad of a board via a brazing material protruding portion such as solder bump without requiring a lead line, and therefore, a wiring length can be reduced. Because of the reasons as mentioned above, cases have increased in which the flip-chip connection is used us a mounting technique of a semiconductor element in an electronic equipment.
At present, solder and Au are generally used as material of a brazing material protruding portion for mounting a semiconductor element onto a board with use of the flip-chip connection. It is noted here that, although Sn—Pb eutectic solder is widely used as a specific material of the solder, the material of the solder is not limited to the Sn—Pb eutectic solder. Other materials such as Sn—Pb (excluding the eutectic solder), Sn—Ag, Sn—Cu, Sn—Zn and Sn—Bi can be used, and further these materials added with a specific additional element such as Ni, Ge and the like can be listed, and one of these materials can be properly selected in accordance with a purpose.
Meanwhile, in many cases of the flip-chip connection of semiconductor element, underfill resin is filled in a gap between a semiconductor element and a board in order to relieve a stress due to a difference in thermal expansion coefficient between the semiconductor element and the board. Thus, reliability of connection can be secured. A mounting structure like this is disclosed in, e.g., Japanese patent publication (JP-A-Heisei 11-233558). Another mounting structure is disclosed in Japanese patent publication (JP-A-Heisei 08-203961) as shown in FIG. 1. In this mounting structure, a conductive metal layer 124 is formed on a surface of a low elastic coefficient layer of a first adhesive layer 123 disposed on an electrode 125 on a board 126 side, and the metal layer 124 is connected with an electrode 121 on a semiconductor element 120 side. This connection is kept with use of a second adhesive layer 122.
Further, in amounting structure disclosed in Japanese patent publication (JP-P2001-185577A) as shown in FIG. 2, a bump 132 is formed on a metal pad 131 of a semiconductor package main body 130, and a metal layer 134 having a melting point lower than that of the bump 132 is formed on an electrode terminal 135 of a board 136, and the bump 132 and the electrode terminal 135 are connected with each other via a conductive adhesive layer 133. Further, in Japanese patent publication (JP-P2000-077558A), there is disclosed a printed wiring board having BGA connection electrodes. Conductive resin is filled into a thorough hole formed in an insulating board from a side of the thorough hole, a BGA connection electrode integrally formed with the same material as that of the conductive resin is provided at the other side of the through hole, and solder resist is formed on at least one surface of the insulating board.
By the way, in the semiconductor element mounting structure disclosed in Japanese patent publication (JP-A-Heisei 11-233558), underfill resin is filled in a gap between the semiconductor element and the board in order to relieve a high stress which is caused by a difference in thermal expansion coefficient between the semiconductor element and the board and which is applied to the solder bump having a high elastic coefficient. However, since a concentrated stress is applied at a connection portion of the bump in a process before filling the resin, it is necessary to take measures against the stress in a manufacturing process. This problem becomes still more serious when a number of products is increased to which a Pb-free solder bump having a high elastic coefficient is applied or when a number of products is increased in which a low-k film (low conductivity film) having a low mechanical strength is used for a chip. Also, even after the underfill resin is filled, an elastic coefficient of the solder bump is much higher than that of the underfill resin. For example, whereas the elastic coefficient of the solder bump of Ag (3 wt % (weight percentage))—Cu (0.5 wt %)—Sn (balance) is approximately 40 GPa (Giga Pascal), the elastic coefficient of the underfill resin is about 10 GPa even in the case of increasing the elastic coefficient by mixing filler thereto. Therefore, there may be a case where the concentrated stress is still applied to the soldering connection portion having a high elastic coefficient, a crack occurs in the solder bump, or a chip or board in the vicinity of the connection portion thereof due to repeated temperature change or the like, the connection reliability cannot be secured as a result.
Therefore, as a trial of lowering an elastic coefficient of a bump joint portion, Japanese patent publication (JP-A-Heisei 08-203961) suggests the structure as shown in FIG. 1 wherein the conductive metal layer 124 is formed surrounding the low elastic coefficient layer of the first adhesive layer 123 on the board side such that the conductive metal layer 124 and the electrode 121 on the semiconductor element side are connected to each other via the second adhesive layer 122. In this case, it is possible to reduce the stress applied to the bump connection portion by using the first adhesive layer 123 having a low elastic coefficient. In this method, however, since the bump 121 on the semiconductor element side is connected with the electrode 125 on the board side via the second adhesive layer 122, it is necessary to strictly control the quantity of the second adhesive layer 122 to be supplied to the respective electrodes 121 and 125. When the quantity of the second adhesive layer 122 is small, it results in a poor connection of the bump. When the quantity is excessive, an excessive adhesive layer spreads from the bump connection portion, which may highly possibly result in a short circuit failure in which neighboring bumps are connected to each other. Moreover, it is necessary to secure the connection by applying some degree of load between the semiconductor element and the board at the mounting of the semiconductor element, and it is a structure in which the first adhesive layer 123 formed on the board side is deformed to be spread at the application of the load and a short circuit failure easily occurs. In view of the above, there is a problem that it is difficult to be applied to a fine pitch structure, and the connection reliability is lowered similarly to the technique disclosed in Japanese patent publication (JP-A-Heisei 11-233558).
In the mounting structure disclosed in Japanese patent publication (JP-P2001-185577A) as shown in FIG. 2, the metal layer 134 having a melting point lower than that of the bump 132 is formed on the electrode terminal 135 of the board 136, and the bump 132 and the electrode terminal 135 are connected with each other via the conductive adhesive layer 133. Hence, when the semiconductor package main body 130 is required to be removed, the semiconductor package main body 130 can be easily removed merely by melting the metal layer 134 of a low melting point, and therefore a purpose of facilitating a rework can be attained. In this mounting structure, since the bump 132 and the electrode terminal 135 are connected with each other via the conductive adhesive layer 133, it is required to take long time to cure the conductive adhesive layer 133 at the connecting. Also, it is necessary to hold the load applied to the semiconductor package main body 130 until the conductive adhesive layer 133 is cured. Unless such processes are carried out, not only the connection reliability is lowered but also a productivity including a connection yield is deteriorated. Japanese patent publication (JP-P2000-077558A) merely discloses the printed wiring board having BGA connection electrodes but does not disclose a mounting structure for flip-chip connecting a semiconductor element to a board.